Add SCTLR bitfield definition for Cortex-R - #317
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Add System Control Register (SCTLR) bitfield definitions for the ARMv8-R architecture, based on the Cortex-R52 Technical Reference Manual. Signed-off-by: Romain Mahoux <romain@mahoux.fr>
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Test Results 256 files - 388 256 suites - 388 0s ⏱️ - 10m 58s Results for commit ae4b5a3. ± Comparison against base commit 4fd64d5. This pull request removes 49 and adds 56 tests. Note that renamed tests count towards both.This pull request removes 5 skipped tests and adds 2 skipped tests. Note that renamed tests count towards both. |
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cc @Masmiseim36 |
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🟢 Approval recommended
The change is a straightforward addition of bitfield macros consistent with existing CMSIS headers and introduces no behavioral logic changes.
Pull request overview
Adds missing System Control Register (SCTLR) bit position/mask macros for the ARMv8‑R (Cortex‑R) profile header, aligning armv8r.h with the existing CMSIS pattern used in other profiles (e.g., armv7r.h, armv8a.h) so consumers can manipulate SCTLR fields via named bit definitions.
Changes:
- Introduces
SCTLR_*_PosandSCTLR_*_Mskmacros for key SCTLR fields inCMSIS/Core/Include/r-profile/armv8r.h. - Covers enable/configuration bits such as TE/EE/FI/UWXN/WXN and cache/MMU related bits (I/C/A/M), plus additional fields like
nTWE,nTWI, andBR.
File summaries
| File | Description |
|---|---|
| CMSIS/Core/Include/r-profile/armv8r.h | Adds ARMv8‑R SCTLR bit position/mask macros to support clearer, safer SCTLR manipulation in user code. |
Review details
- Files reviewed: 1/1 changed files
- Comments generated: 0
- Review effort level: Lite
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Add System Control Register (SCTLR) bitfield definitions for the ARMv8-R architecture, based on the Cortex-R52 Technical Reference Manual.