ECE undergrad at VIT Vellore. Mostly working on computer architecture, digital design (SystemVerilog/RTL), and embedded systems firmware.
-
NeuroCore-32
5-stage pipelined RV32I processor in SystemVerilog. Implements EX/MEM data forwarding, load-use hazard detection, a 2-bit branch predictor with a 16-entry BTB, and hardware performance counters. Verified benchmark execution on ModelSim and Xcelium (~95% branch accuracy, 0.84–0.99 IPC) and synthesized on an Intel Cyclone V FPGA (314 MHz). -
Semantic-Data-Prefetcher
Hardware N-gram delta prefetcher that learns non-strided access patterns (pointer chasing, linked lists). Built a 32 KB L1 cache simulator in Python to benchmark against classic stride prefetchers, along with a synthesizable SystemVerilog RTL implementation (1024-entry SRAM table, 2-bit confidence FSM). -
BioPatch Pro
Wearable physiological monitor tracking hydration, thermal stress, and fatigue using electrodermal (GSR) and temperature sensors. Firmware runs on an ESP32 with VPD-aware recursive inverse filtering and streams live telemetry to Firebase. -
RTL & Embedded Modules:
- sv-uart: Parameterized UART TX/RX controller with configurable baud generator.
- sv-fifo: Synchronous and dual-clock asynchronous FIFOs using Gray code pointers.
- Embedded-C_STM32: Bare-metal register-level peripheral drivers (GPIO, USART, Timers, I2C, SPI) on ARM Cortex-M.
- MAC_CRYPTO_64BIT: Pipelined 64-bit Multiply-Accumulate unit with overflow saturation.
- Advanced Vedic Multipliers: 32/64-bit Vedic multipliers using Carry Select Adders.
- Design of 32 and 64-bit Advanced Vedic Multipliers using CSLA and Analyzing Delay, Power and Area
2026 International Conference on Next Generation Electronics (NELEX), Vellore, India
DOI: 10.1109/NELeX69209.2026.11590629
- HDLs & Design: SystemVerilog, Verilog, RTL design, pipelining, FSMs
- EDA & Synthesis: ModelSim, QuestaSim, Xcelium, Intel Quartus Prime, Xilinx Vivado
- Embedded & Protocols: ARM Cortex-M (STM32), ESP32, Bare-metal C, CAN, I2C, SPI, UART
- Other: Python, C/C++, Linux, Git