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altera

Here are 271 public repositories matching this topic...

pConst / basic_verilog

Must-have verilog systemverilog modules

Updated Mar 12, 2026
Verilog

hdl-util / hdmi

Send video/audio over HDMI on an FPGA

audio video fpga intel xilinx vivado altera hdmi systemverilog dvi quartus hdlmake

Updated Jul 13, 2026
SystemVerilog

olofk / edalize

An abstraction library for interfacing EDA tools

Updated Aug 12, 2026
Python

VLSI-EDA / PoC

The PoC Library has been forked to github.com/VHDL/PoC. See new address below

Updated Jul 30, 2025
VHDL

f32c / f32c

A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz

arduino fpga mips riscv xilinx altera lattice

Updated Sep 3, 2026
VHDL

hdl-modules

hdl-modules / hdl-modules

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Updated Jul 27, 2026
VHDL

OpenFPGAduino / OpenFPGAduino

All open source file and project for OpenFPGAduino project

nodejs javascript c iot arduino arm opensource fpga cpp hardware verilog blockly grove-shield iiot altera

Updated Oct 27, 2018
Makefile

drandyhaas / Haasoscope

Docs, design, firmware, and software for the Haasoscope

python open-source fpga eagle open-hardware data-acquisition verilog oscilloscope altera

Updated Jun 6, 2026
Verilog

hftrx

ua1arn / hftrx

Embedded firmware for ham radio transceivers

zynq stm32 ham-radio sdr altera hdmi bare-metal baremetal hamradio allwinner ssb cortex-a53 cortex-a7 ehci stm32mp1 sdr-radio t113-s3 cortex-a55 cortex-a76

Updated Sep 4, 2026
C

awesome-fpga-boards

iDoka / awesome-fpga-boards

🏧 Second life for FPGA boards which can be repurposed to DYI/Hobby projects ...............................................................................................

microsoft awesome fpga zynq intel xilinx awesome-list ethernet altera lattice jtag bmc antminer qsfp pci-e ecp5 colorlight chubby75

Updated Jan 12, 2021

hukenovs / intfftk

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

fpga dsp vhdl verilog fast-fourier-transform xilinx fft vivado altera cooley-tukey-fft digital-signal-processing fast-convolutions radix-2 integer-arithmetic route-optimization

Updated Jan 31, 2023
VHDL

thinkoco / c5soc_opencl

DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on.

fpga opencl mandelbrot altera de1-soc vga sobel usb-cameras intelfpga de10-nano

Updated Nov 7, 2020
Verilog

BrianHGinc / BrianHG-DDR3-Controller

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

fpga intel verilog xilinx altera systemverilog lattice hdl testbenches ddr3

Updated Apr 8, 2024
SystemVerilog

VHDL / PoC

IP Core Library - Published and maintained by the Open Source VHDL Group

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Updated Jul 14, 2026
VHDL

halfmanhalftaco / fpga-docker

Tools for running FPGA vendor toolchains with Docker

fpga vhdl verilog xilinx altera lattice quartus

Updated Apr 30, 2023
Makefile

mithro / ixo-usb-jtag

usb-jtag - Altera USB Blaster Emulation with a FX2

fpga xilinx altera usb-devices openocd jtag numato-opsis digilent-atlys cypress-fx2 ezusb digilent opsis numato urjtag

Updated Nov 2, 2025
C++

anthony-bernaert / ftdi-jtag-programmer

FTDI-based JTAG Programmer Circuit for FPGAs

fpga usb programmer xilinx uart altera ftdi lattice jtag serial-port intel-fpga pcb-design

Updated Jun 3, 2025

MJoergen / HyperRAM

Portable HyperRAM controller

fpga vhdl intel xilinx vivado altera lattice modelsim questasim avalon quartus artix questa hyperram

Updated Dec 8, 2024
VHDL

hukenovs / fp23fftk

Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).

Updated Jul 5, 2022
VHDL

suoto / vim-hdl

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

productivity vhdl vim-plugins verilog xilinx syntastic syntax-checker altera systemverilog modelsim

Updated Jun 1, 2021
Python

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