isa
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RISC-V: Open-source instruction set architecture based on reduced instruction set computer principles.
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Apr 2, 2026
F# RISC-V Instruction Set formal specification
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Jun 12, 2026 - F#
Browser-based Arm micro-architecture simulator with single-cycle and pipelined CPU visualization (educational, simulator)
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Jun 13, 2025 - JavaScript
RTL8019-based ISA network card, NE2000-compatible
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Mar 19, 2021 - HTML
Verilog Implementation of an ARM LEGv8 CPU
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Oct 3, 2018 - Verilog
For finding, sharing and exchanging Data, Models, Simulations and Processes in Science.
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Sep 3, 2026 - Ruby
ISA 8bit sound card based on the ES1868F sound chip, providing Sound Blaster PRO and OPL3 compatibility in a highly integrated package
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Jul 6, 2026
A technical checklist to spark curiosity and reflection when designing software systems.
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Jan 9, 2022 - SCSS
ISA tools API
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Sep 1, 2026 - Python
Sound Card for the ISA (8bit) bus sporting Sound Blaster / Sound Blaster PRO emulation via ES688F chip, and a real Yamaha OPL3 FM Synth. It's also completely jumper configurable.
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Jul 6, 2026
Tool for creating and editing annotation tables in ARCs.
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Sep 4, 2026 - F#
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