VU13P FPGA MIPI CSI-2 验证框架(纯 RTL):Vivado BD + mipi_sys_ctrl + PySide6,2-Lane RAW10(IMX298)
python fpga camera rtl verilog xilinx vivado uart hardware-testing fpga-development mipi csi-2 pyside6 bring-up sensor-validation xilinx-ultrascale imx298 vu13p sensor-test-framework
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Updated
Jun 26, 2026 - Verilog