DNS stub resolver, proxy and router with support for DoT, DoH, DoQ, and DTLS
Education kit for teaching computer architecture with a 5-stage Arm-based Verilog core and hands-on labs (educational)
The Refreshingly Simple Cross-Platform C++ Dataflow / Patching / Pipelining / Graph Processing / Stream Processing / Reactive Programming Framework
Multi-device OpenCL kernel load balancer and pipeliner API for C#. Uses shared-distributed memory model to keep GPUs updated fast while using same kernel on all devices(for simplicity).
Cross-Platform Graphical Tool for DSPatch
MIT Course 6.004 - Computation Structures
ANPS-TradeMeUp is an LLM-powered AI News Prediction System for short-to-medium term market forecasting, featuring real-time analysis and a Dash-based monitoring dashboard.
Asynchronous, HA (master-master) PostgreSQL driver on top of libpq.
Verilog synthesis directly from idiomatic Python for numerical/DSP-heavy applications. Not an HDL.
Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic
DSPatch Component Repository
Efficiently pipeline, batch, and cache requests to any data source
A two-stage predictive machine learning engine that forecasts the on-time performance of flights for 15 different airports in the USA based on data collected in 2016 and 2017.
FluidML is a lightweight framework for developing machine learning pipelines.
Kite: Architecture Simulator for RISC-V Instruction Set
A 5-stage pipelining RISC-V 32I simulator written in Rust.
An experiment in declaratively programming parallel pipelines of state machines.
Design and verification of a simple pipelined RISC processor in Verilog, featuring a five-stage pipeline and custom ISA.
Educational computer simulator on a mission to "superscale" the study of computer architecture fundamentals
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